1. Field of the Invention
The present invention relates to a semiconductor memory device such as a DRAM, and a method of preventing a latch error in the same.
2. Description of the Related Art
Recently, a semiconductor memory device, e.g. a double data rate type a dynamic random access memory of (to be referred to as a DDR DRAM) is used mainly. Also, a synchronous DRAM in which a read and write operations are synchronous with a clock signal (to be referred to as an SDRAM) is popular.
FIG. 1 is a block diagram showing the configuration of a conventional DDR DRAM. Referring to FIG. 1, the conventional DDR DRAM is provided with an address circuit, a command circuit, a memory cell array 15, a data circuit and a clock circuit. The address circuit is composed of an address terminal group 10, an address input circuit 11, an address latch circuit 12, an address buffer circuit 13, and an address decoder 14. The command circuit is composed of a command terminal group (/CS, /RAS, /CAS, and /WE) 17, a command input circuit 18, a command decoder & mode register 19, a control circuit (1) 20, and a control circuit (2) 21. The clock circuit is composed of a clock terminal group (CK, /CK) 22 and 23, a clock input circuit & internal clock signal generating circuit 24, and a DLL circuit 25. The data circuit is composed of a data terminal (DQ) 26, a data strobe terminal (DQS) 27, a reference voltage (Vref) terminal 28, a data signal input circuit 30, a data strobe signal input circuit 31, a data latch circuit 32, a data signal output circuit 33, a data strobe signal output circuit 34, a data buffer & data amplifier 29, and a sense amplifier circuit 16. Although a plurality of data terminals may be provided, only one of the data terminals is shown here for convenience.
An address is supplied to the address input circuit 11 through the address terminal group 10, and then is latched by the address latch circuit 12. A part of the latched address is supplied to the command decoder and mode register 19. The latched address is supplied to the decoder 14 through the address buffer 13 and decoded and supplied to the memory cell array 15. The memory cell array 15 has memory cells arranged in a matrix and one of rows of memory cells is designated based on the decoded result. A command is supplied to the command decoder & mode register 19 through the command input terminal group 17 and the command input circuit 18. The command decoder & mode register 19 receives the address from the address latch circuit 12 and an internal clock signal (ICK) S1 from the input circuit & internal clock signal generating circuit 24 in addition to the command and outputs control signals to the control circuits 20 and 21. External clock signals CK and /CK are supplied to the clock input circuit & internal clock signal generating circuit 24 and the DLL circuit 25 through the external clock signal terminals 22 and 23. The clock input circuit & internal clock signal generating circuit 24 generates internal clock signal (ICK and /ICK) S1 and S2, and outputs the internal clock signal (ICK) S1 to the command decoder & mode register 19, the address latch circuit 12, the control circuit 21 and the data latch circuit 32, and the internal clock signal (/ICK) S2 to the data latch circuit 32. The DLL circuit 25 outputs a synchronous signal to the data signal output circuit 33 and the data strobe signal output circuit 34. The control circuit 20 outputs control signals to the address buffer 13 and the sense amplifier circuit 16. The control circuit 21 outputs control signals to the address buffer 13, the data buffer and data amplifier 29, the data signal output circuit 33 and the data strobe signal output circuit 34, and the data signal input circuit 30 and the data strobe signal input circuit 31. The data strobe signal input circuit 31 receives a data strobe signal and outputs it to the data latch circuit 32 as a signal S4. The data signal input circuit 30 receives an external data signal and outputs it to the data latch circuit 32. The data latch circuit 32 receives the data signal in response to the data strobe signal and outputs to the data buffer and data amplifier 29. The sense amplifier circuit 16 writes the data signal received from the data amplifier 29 through the sense amplifier circuit 16 into one memory cell of the memory cell array 15. A data signal read out from the memory cell array 15 by the sense amplifier circuit 16 is supplied to the data signal output circuit 33 through the data buffer and data amplifier 29. The data signal output circuit 33 outputs the read-out data signal through the terminal 26, and the data strobe signal output circuit 34 outputs the data strobe signal through the terminal 27. A reference voltage (Vref) terminal 28 is connected to the data signal input circuit 30, the data strobe signal input circuit 31, the address input circuit 11, and the command input circuit 18.
A typical operation of each section in the DDR DRAM will be described below briefly, because it is well known to a person in the art. The internal clock signals (internal ICK signal S1, internal /ICK signal S2) are generated by the clock input circuit & internal clock signal generating circuit 24 from external clock signals CK and /CK supplied through the clock signal terminals 22 and 23. The address signal is supplied to the address terminal group 10, passes through the input circuit 11 and then is latched by the address latch circuit 12 in response to the internal clock signal S1. Then, the address is generated and outputted to the memory cell array 15 from the address buffer 13 and the address decoder 14. The command signal is supplied to the command terminal group 17, and passes through the command input circuit 18 to the command decoder & mode register 19. Then, signals for various operations are generated by the command decoder & mode register 19 in synchronous with the internal clock signal ICK S1. Further, instruction or control signals for the various operations are generated by the control circuit 20 and the control circuit 21. In a write operation, the data signal is supplied to the data signal input circuit 30 and latched by the data latch circuit 32 in response to the output signal S4 from the data strobe signal input circuit 31. Then, this data signal is written into the memory cell of the memory cell array 15 from the data buffer 29. In a read operation, the data signal in the memory cell is amplified by the sense amplifier circuit 16 and the data amplifier 29, and then this data signal is outputted to the data terminal 26 from the data signal output circuit 33 in response to an output signal of the DLL circuit 25.
The data strobe signal terminal 27 is provided in the DDR DRAM for the following reasons. In the DDR DRAM, the data effective width is only 0.5 clock period which is a half of the data effective width in a conventional SDRAM. There is usually a signal timing difference in data transfer between a memory and a memory controller, thereby reducing a timing margin. Thus, as the clock period becomes faster, the timing margin for data latch becomes smaller. For this reason, a data strobe (DQS) terminal 27 is provided for a data latch signal. The data latch signal is used in a write operation, as a signal for latching the data signal on the data terminal 26 in the DDR DRAM. In a read operation, the data latch signal is outputted from the DDR DRAM in synchronization with the data signal outputted from the data terminal 26, and is used as a signal for latching the data signal on the data terminal on the memory controller side.
FIGS. 2A to 2J are timing charts showing signal waveforms of various sections of the DDR DRAM in the write operation the read operation when the burst length is 4. Referring to FIGS. 2A to 2J, the waveforms of the signals on the data terminal 26 and the data strobe terminal 27 in the write and read operations will be described below.
In the write operation, as shown in FIG. 2D, the data strobe signal on the data strobe terminal 27 goes to a low level a predetermined time after a write command shown in FIG. 2C is received. This initial low level period is called a preamble period. Subsequently, the data strobe signal on the data strobe terminal 27 toggles between the high level and the low level in accordance with data D1, D2, D3, and D4 on the data signal. An input setup time and an input hold time are set for each of data D1 to D4, as shown in FIG. 2E. In response to the data strobe signal on the data strobe terminal 27 which goes to a high level, the data D1 is latched. The data strobe signal is lastly changed from the low level state to a high impedance state when the input of the last data D4 is completed. This last low level state is called a postamble state. In the read operation, after a read command (READ) shown in FIG. 2H, four bursts of data D1, D2, D3, and D4 are outputted from the data terminal 26, following the CAS latency which is set in the mode register 19 based on a mode set command, as shown in FIG. 2J. The data strobe signal on the data strobe terminal 27 is toggled in synchronization with the clock signal after a preamble period, as shown in FIG. 2I, and then the data strobe terminal 27 returns to a high impedance state through the postamble state.
Next, the data circuit will be described. FIG. 3 is a block diagram showing the configuration of the data circuit. The data circuit includes the data signal (DQ) input circuit 30, the data strobe signal (DQS) input circuit 31, and the data latch circuit 32. The data latch circuit 32 includes D-type flip-flop circuits 321, 322, 323, 324, and 325. The data signal input circuit 30 and the data strobe signal input circuit 31 receives an input control signal S5 from the control circuit 21. Also, the data signal input circuit 30 receives the data signal (DQ) and the reference voltage signal (Vref), and the data strobe signal input circuit 31 receives the data strobe signal (DQS) and the reference voltage signal (Vref). The output of the data signal input circuit 30 is connected to data (D) terminals of the D-type flip-flop circuits 321 and 324, and the output of the data strobe signal input circuit 31 is connected to clock (C) terminals of the D-type flip-flop circuits 321 and 324. Here, the clock terminal of the flip-flop 324 receives the data strobe signal by inverting it. The data output terminal of the D-type flip-flop circuit 321 is connected to the data terminal of the D-type flip-flop circuit 322, and the data output (Q) terminal of the flip-flop circuit 322 is connected to the data terminal of the D-type flip-flop circuit 323. The data output terminal of the flip-flop circuit 323 is outputted to a data line (1). Also, the data output terminal of the D-type flip-flop circuit 324 is connected to the data terminal of the D-type flip-flop circuit 325. The data output terminal of the flip-flop circuit 325 is outputted to a data line (2). The internal clock signal /ICK S2 is supplied to the clock terminal of the D-type flip-flop circuit 322, and the internal clock signal ICK S1 is supplied to the clock terminals of the D-type flip-flop circuits 323 and 325.
The data signal input circuit 30 and the data strobe signal input circuit 31 are formed as shown in FIG. 4. The input circuit 30 or 31 includes P-channel MOS transistors 100, 101, and 105, N-channel MOS transistors 102, 103, and 104, and an inverter 106. The P-channel MOS transistor 100 and the P-channel MOS transistor 101 form a current mirror circuit. The N-channel MOS transistors 102 and 103 form a differential transistor pair. The P-channel MOS transistor 100 and the N-channel MOS transistor 102 are connected in series. Similarly, the P-channel MOS transistor 101 and the N-channel MOS transistor 103 are connected in series. The N-channel MOS transistor 104 is provided between the ground and a common emitter node between the N-channel MOS transistor 102 and the N-channel MOS transistor 103. Further, the P-channel MOS transistor 105 and the inverter 106 are connected in series such that a node between the P-channel MOS transistor 101 and the N-channel MOS transistor 103 is connected to a node between the P-channel MOS transistor 105 and the inverter 106. The reference voltage signal Vref and an input signal (the data signal or the data strobe signal) are supplied to the gates of the N-channel MOS transistors 102 and 103, respectively, and the input control signal is supplied to the gate of the N-channel MOS transistor 104 and the gate of the P-channel MOS transistor 105. Therefore, if the data strobe signal as the input signal has a glitch, the voltage of the drain of the N-channel MOS transistor 103 is changed in response to the glitch, and a pulse signal is generated by the inverter circuit 106.
FIG. 5 shows each of the D-type flip-flop circuits 321, 322, 323, and 325, and is composed of transfer gates 110, 111, 112, and 113, and inverters 114, 115, 116, 117, and 118. FIG. 6 shows the D-type flip-flop circuit 324 and is composed of transfer gates 119, 120, 121, and 122, and inverters 123, 124, 125, 126, and 127.
The data signal input circuit 30 and the data strobe signal input circuit 31 are activated in the write operation. FIG. 7 is a block diagram showing the configuration of a part of the control circuit 21 as an input control signal generating circuit that generates the input control signal S5, and includes a write control circuit 1, a NOR circuit 2, and an inverter circuit 3. The write control circuit 1 receives a write command signal, various mode signals, the internal clock signal ICK S1, and write control signals, and outputs an input control signal S9. The NOR circuit 2 receives the input control signal S9 and the write control signal S10 as one of the write control signals. The inverter circuit 3 inverts the output of the NOR circuit 2 and output a DQ/DQS input control signal S5.
Next, referring FIGS. 8A to 8R, an operation of the input control signal generating circuit shown in FIG. 7 will be described in detail. FIG. 8A shows an external clock signal CK, and FIG. 8B shows another external clock signal /CK that is obtained by inverting the clock signal CK. In the DDR DRAM, in response to the CK and the /CK, the clock input circuit & internal clock signal generating circuit 24 generates an internal clock signal ICK S1 that is synchronous with the rising edge of the clock signal CK and the falling edge of the clock signal /CK, as shown in FIG. 8F, and an internal clock signal /ICK S2 that is synchronous with the falling edge of the clock signal CK and the rising edge of the clock signal /CK, as shown in FIG. 8G. When a write command (WRITE) is inputted at a time t0 as shown in FIG. 8C, a write command signal is generated by the command decoder 19 in response to the rising edges of the internal clock signal ICK, as shown in FIG. 8H. The input control signal S9 is generated in response to the rising edges of the internal clock signal ICK, based on a mode signal indicating the burst length and generated by the mode register 19 in response to a mode set command, as shown in FIG. 8I, and the signal width of the input control signal S9 is equivalent to clock periods corresponding to a half of the burst length. Also, a write control signal S10 is generated as shown in FIG. 8J by delaying the input control signal S9 by a summation of clock periods corresponding to the write latency and one clock period. The write control signal S10 is activated during a period when data is written into the memory cell array 15.
In FIGS. 8A to 8R, the burst length is 4 and the write latency is 1. Thus, the input control signal S9 shown in FIG. 8I has the signal width of 2 clock periods, and the write control signal S10 shown in FIG. 8J is a signal obtained by delaying the input control signal S9 by 2 clock periods. A DQ/DQS input control signal S5 shown in FIG. 8K is generated based on the input control signal S9 and the write control signal S10 by the NOR circuit 2 and the inverter circuit 3. Thus, when at least one of the input control signal S9 shown in FIG. 8I and the write control signal S10 shown in FIG. 8J is in the high level, the DQ/DQS input control signal S5 shown in FIG. 8K is in the high level.
An output of the input circuit shown in FIG. 4 is fixed to a low level when an input is in the low level, whereas when the input is in the high level, a differential amplifier circuit, composed of the P-channel MOS transistors 100 and 101 and the N-channel MOS transistors 102, 103, and 104, compares the input voltage level with the voltage level Vref on the reference voltage terminal 28 to generate an output signal. Specifically, as shown in FIGS. 8A to 8R, in the data signal and data strobe signal input circuits, when the input control signal S5 shown in FIG. 8K is in the low level, an input circuit output signal 53 shown in FIG. 8M and an input circuit output signal S4 shown in FIG. 8L are fixed to the low level, whereas when the input circuit control signal S5 shown in FIG. 8K is in the high level, the input circuit output signal S3 shown in FIG. 8M and the input circuit output signal S4 shown in FIG. 8L change as a result of input of the data signal and the data strobe signal. Next, in the write operation, the data D1 is supplied from the data terminal 26 to the data latch circuit 32 as the input circuit output signal S3 shown in FIG. 8M. That is, in more detail, the input circuit output signal S3 is supplied to the D-type flip-flop circuit 321, latched by it in response to the rising edge of the input circuit output signal S4 shown in FIG. 8L, and outputted as the signal S6 shown in FIG. 8N. Subsequently, the data signal S6 shown in FIG. 8N is latched again by the D-type flip-flop circuit 322 in response to the rising edge of the internal clock signal /ICK S2 shown in FIG. 8G, transferred as a signal S8 shown in FIG. 8P to the D-type flip-flop circuit 323, then latched in response to the rising edge of the internal clock signal ICK S1 shown in FIG. 8F, and transmitted onto the data line (1) shown in FIG. 8Q. The data D3 is also processed in the same manner, Meanwhile, the data D2 is supplied from the data terminal 26 to the D-type flip-flop circuit 324 as the data signal input circuit output signal S3 shown in FIG. 8M, and latched by the D-type flip-flop circuit 324 in response to the falling edge of the input circuit output signal S4 shown in FIG. 8L. The data output terminal signal as a signal S7 shown in FIG. 8O is latched by the D-type flip-flop circuit 325 in response to the rising edge of the internal clock signal ICK S1 shown in FIG. 8F, and then transmitted to the data line (2) shown in FIG. 8R.
Next, an operation will be described in a case that the data strobe signal has a glitch on the change of the output from the postamble period state to the high impedance state. Referring to FIGS. 9A to 9N, a glitch waveform in the write operation appearing when the data strobe signal is reset to the high impedance state after the postamble period will be described in detail.
Portions surrounded by circles of dotted line shown in FIG. 9D shows a glitch waveform of the data strobe signal. The data strobe signal input circuit 21 generates the glitch waveform at around a time t6, and changes the data strobe signal input circuit output signal S4 shown in FIG. 9H at around the time t6. In the DDR DRAM, the data strobe signal is permitted to shift from side to side with respect to the external clock signal CK. Thus, the shift of 0.3 clock period is permitted in the DDR DRAM called DDR 1. FIG. 9D is a timing chart showing the signal waveform of the data strobe signal being shifted to the left with respect to the CK so that a malfunction due to the data strobe glitch waveform is likely to occur.
The data signal S3 is supplied to the data signal terminal 26 and latched by the D-type flip-flop circuits 321, 322, and 324 in order as mentioned above. Also, the data signal S3 is latched by the D-type flip-flop circuits 324 and 325 in order as mentioned above. However, the signal S3 is latched by the D-type flip-flop circuit 324 in response to the rising edge of the data strobe signal input circuit output signal S4 shown in FIG. 9H. For this reason, a latter half of the data D4 is latched again in response to the glitch waveform to be overwritten, as shown in FIG. 9K. Therefore, the data D1 and D3 are transferred to the data line (1) as shown in FIG. 9M in response to the rising edge of the next internal clock signal ICK S1 shown in FIG. 9F. Also, the data D2 is properly transferred to the data line (2) as shown in FIG. 9N although the overwritten data D4 is not transferred thereto. Therefore, a problem is caused that the data D1, D2, and D3 are properly written into the memory cells, but the data D4 is not properly written into the memory cell.
In conjunction with the above description, Japanese Patent No. 3317912 discloses a semiconductor memory device. In this conventional example of the semiconductor memory device, a synchronization signal input section inputs a synchronization signal for data acquisition and outputs an internal synchronization signal. An acquiring section acquires data in synchronous with the internal synchronization signal. A storing unit stores the data. A control section sets the synchronization signal input section to an enable state or a disable state in response to input of a write command for writing the data into the storing unit. The control section sets the synchronizing signal input section to the enable state to output the internal synchronization signal, when the write command is inputted, and also starts counting the number of clock of the internal synchronization signal. Also, the control section sets the synchronizing signal input section to the disable state when the count reaches a certain reference number of times.
Japanese Laid Open Patent Application (JP-P2000-156083A) discloses a semiconductor device. In this conventional example of the semiconductor device, a serial data signal as external data signals is successively latched in synchronization with a data strobe signal. Also, the latching of the serial data signal in the internal circuit is inhibited in response to a timing of change in the data strobe signal corresponding to the final bit of the serial data signal.
Japanese Laid Open Patent Application (JP-P2003-59267A) discloses a semiconductor memory device. In this conventional example of the semiconductor memory device, 2N (N is natural number) data signals are successively received in synchronization with N pairs of leading and trailing edges which are contained in an external clock signal. Also, an external data strobe signal has the N pairs of leading and trailing edges in synchronization with the 2N data signals and is set to a reference voltage after the passage of the postamble period following the last trailing edge. The 2N data signals are latched in synchronization with the N pairs of leading and trailing edges which are contained in the external data strobe signal. Further, in the semiconductor memory device, an input buffer outputs an internal data strobe signal in accordance with the external data strobe signal. A gate circuit receives the internal data strobe signal outputted from the input buffer and inhibits the passage of the internal data strobe signal in response to inactivation of a first control signal. A latch circuit sequentially latches the 2N data signals in response to each of the leading and trailing edges contained in the internal data strobe signal that has passed through the gate circuit. A control circuit sets the first control signal to an inactivated level in response to the Nth trailing edge included in the internal data strobe signal.
As described above, a conventional input control circuit suffers from a problem that, when a data strobe signal is received in a manner to be shifted with respect to the clock signal CK, a proper data signal cannot be written into a memory cell. The cause of the occurrence of this problem is as follows. This is because the data strobe signal input circuit operates in response to a glitch waveform after the postamble of the data strobe signal.
In conjunction with the above description, a semiconductor memory device is disclosed in Japanese Laid Open Patent application (JP-P2003-272379A). In this conventional example, a memory cell array is provided. A clock generating circuit generates first and second internal clock signals in synchronization with the rising and falling edges of an external clock signal. A clock selecting circuit selects as a first operation clock signal, one of the first and second internal clock signals in accordance with the number of cycles from reception of a data read command from the memory cell array to start of output of the read data from the memory cell array, and selects the other as a second operation clock signal. One or more signal recovering circuits recover a signal outputted from the clock selecting circuit. An output circuit outputs the read data in synchronization with the first and second clock signals which are subjected to the recovery by the signal recovering circuits.